To compete with the upcoming Epyc 2 processors, Intel today introduced new Xeon processors called Cascade Lake-AP with 48 cores and MCM design.
Intel finally with MCM design?
Multi chip modules, MCM for short, seem to be the next step to make processors even better. There is not one monolithic die that houses all processor cores, but several dies that are connected to an interposer. This interposer then handles the entire communication between the individual dies. While Intel has always relied on a monolithic design in recent years, the major upheaval came from its competitor AMD. With the Zen architecture, AMD also introduced the first MCM processors for the server sector. In the first generation of Epyc, codenamed Naples, four dies with up to eight cores each are in use. In this way, 32 cores are possible, but an Epyc processor can be produced much more easily in comparison. Poorer Zen dies can also be used in other AMD products such as the Ryzen processors. But there are also disadvantages. Memory communication is often much slower, for example.
With the new Epyc generation, codenamed Rome, AMD improves the design once again and could rely on eight eight-core dies with a central management chip for memory and I/O management. As a result, the latency times are the same for all cores. The procedure with the MCM processors had already been mocked by Intel several times. Epyc was called a ” glued together desktop processor “. However, Intel relies now on a MCM design itself. This is especially necessary because progress in even smaller manufacturing processes is stagnating.
Cascade Lake-AP comes with 48 cores on two dies
The newly introduced processor generation is called Cascade Lake-AP. The AP stands for “Advanced Processors”. There are not many changes in the architecture compared to Skylake-SP. Intel continues to rely on 14nm production. Instead of one die, two dies with 24 cores each are used on one processor package. These are connected to the company’s Ultra Path Interconnect interface (UPI). Intel emphasizes that the already existing EMIB interposer is not used here, which for example in Kaby Lake-G provided the connection with the Vega graphics unit. UPI is the successor of QPI and is normally used for multi-socket systems. The Cascade Lake-AP processor has a total of 12 memory channels due to its structure with two dies. Each die can address six channels. Due to the enormous size of the two dies and the twelve channel interface, a new socket and more contacts are needed.
It is currently still unclear whether the 48-core is the largest version. In addition to the large MCM processor, there are also new Cascade Lake-SP processors, which are a Skylake-SP refresh with up to 28 cores. A processor with a total of 56 cores would also be possible with two 28-core dies. Whether Intel will realize such an expansion stage will probably only be seen in 2019. Then the first processors will be presented again in detail at a larger launch event. The first Cascade Lake SP processors are scheduled for delivery in 2018. Unknown at the moment are the prices Intel is calling. By the way, there will be an event tomorrow at which AMD will present the new Epyc 2 processors with 64 cores. The timing is reminiscent of Computex, where Intel’s 28-core desktop processor was eclipsed the next day by AMD’s second generation of threadripper processors with up to 32 cores.